This invention relates to a multi-slope integrating analog-to-digital converter which integrates input analog signals during a first integration period, during which a first reference signal of opposite polarity to the input signal is integrated repeatedly together with the input analog signal so as to cause a predetermined number of cycles of rising and falling at the integrator output, after which a second reference signal and a third reference signal are integrated during respective second and third integration periods, to obtain a digital signal corresponding to an input analog signal by measuring the time intervals of the first reference signal being integrated and the second and third integration periods.
A dual-slope type integrating analog-to-digital converter is well known in the art. In such an analog-to-digital converter, an input signal is provided to an integrator and is integrated during the first integration period T.sub.1, resulting in a rising slope being output from the integrator as shown in FIG. 1. At the end of the first integration period T.sub.1, a reference signal of opposite polarity to the input signal is provided to the integrator so as to cause a falling slope at the integrator output. As illustrated in FIG. 1, a second integration period T.sub.x begins at a time when the reference signal integration starts, and ends at the time when the integrated signal reaches a predetermined voltage level, for example, the voltage level at the beginning of the integration, which is typically provided to be ground potential.
When the input analog signal is small, the integrated output at the end of the first integration period T.sub.1 is small because the first integration period is fixed, and thus the second integration period T.sub.x becomes short as shown by the broken line in FIG. 1. In other words, the second integration period T.sub.x depends on the voltage level of the input analog signal. The second integration period T.sub.x is measured for example by a counter, and accordingly the measured digital data corresponds to the value of the input analog signal.
A prior art triple-slope analog-to-digital converter is described in U.S. Pat. No. 3,577,140, in which an input signal to be measured is integrated for a fixed period, and then the integrated value is down-counted to a predetermined level while applying a reference signal, followed by completing the down-counting into a less significant digit while applying a smaller reference signal. U.S. Pat. No. 4,354,176 describes an analog-to-digital converter that for instance avoids inaccuracies due to reaching said predetermined level during the middle of a clock pulse.
In such known analog-to-digital converters, a voltage supplied across an integrating capacitor increases when the input analog voltage increases, resulting in the so-called dielectric absorption problem. The dielectric absorption problem concerns a degrading of the linearity of the voltage charged in the integrating capacitor when a high voltage is supplied to the integrator. Thus analog to digital conversion with high accuracy is difficult with this prior art.
For solving this problem, a multi-slope integrating analog-to-digital converter is known, for instance as described at page 9 of the Hewlett-Packard Journal of February 1977. FIG. 2A is a block diagram of such a prior art example of a multi-slope analog to digital converter, and FIG. 2B is a voltage-time diagram of the multi-slope analog-to-digital converter of FIG. 2A. According to this multi-slope analog-to-digital converter, within the first integration period T.sub.1 a first reference signal, of opposite polarity to the input analog signal and of greater absolute value than the maximum input analog signal to be measured, is applied to the integrator 14 each time the integrator signal reaches a predetermined voltage V.sub.1. The comparator 24T in FIG. 2A is used for sensing the integrated signal crossing the voltage level V.sub.1.
Thus the output from the integrator 14 begins to fall as in FIG. 2B and, after the fixed time interval T.sub.3, the first reference signal is stopped from supplying the integrator 14 in order to integrate the input signal alone. The integrated signal again begins to rise and, when it reaches the predetermined voltage V.sub.1 again, the first reference signal is again integrated together with the input signal during the subsequent fixed period T.sub.3.
This process is repeated during the first integration period T.sub.1, and, after the first integration period T.sub.1, the second reference signal I.sub.2, of opposite polarity from the integrated signal at the end of the first integration period T.sub.1, is provided to the integrator 14 so that the second integration T.sub.x begins. The second integration period T.sub.x ends when the integrated signal crosses the predetermined voltage level in the same way as the dual-slope analog-to-digital converter. For the T.sub.x and the T.sub.3 periods, digital signals are obtained for providing a digital value corresponding to the input analog signal.
According to this prior art multi-slope integrating analog-to-digital converter, since the integrating capacitor is not supplied with a voltage higher than V.sub.1, the linearity error originating from the dielectric absorption problem does not occur. However, when the input analog signal is small, the number of times the fixed integration period T.sub.3 occurs within the first integration period is reduced, as shown by the broken line in FIG. 2B. Because the slope of the integrated output is lower, it takes a longer time to get to the voltage V.sub.1, and conversely, when the input analog signal is increased, the number of times of the period T.sub.3 occurs is also increased. Therefore, according to the voltage level of the input analog signal, there is a variation in the number of times the integration period T.sub.3 occurs, that is, during which both the input signal and the first reference signal are integrated.
The first reference signal I.sub.1 is provided to the integrator 14 through a switch 17 as illustrated in FIG. 2A, and the switch 17 has a delay time when it is closed or opened by a control signal, and thus an error caused by these delay times is included in the time period T.sub.3. It is possible to compensate for this error if it is always the same. However, the error varies in accordance with the level of the input analog signal, since the number of times the switching operation occurs depends on the voltage level of the input signals. Accordingly, compensation for the error caused by this switching delay time is not feasible in this prior art multi-slope integrating analog-to-digital converter. This error is especially damaging in high speed analog-to-digital conversion.